It is often desirable to synchronize two or more electronic devices to facilitate an exchange of data between such devices. Such devices, for example, may include integrated circuit (IC) chips, components or other electronic devices. These and other devices can be coupled to each other in a given circuit board or via other connections over a plurality of circuit boards to form an integrated system. Effective synchronization is needed to enable transfer of data (e.g., input/output (I/O) data) between devices. If the devices are not sufficiently synchronized, the transfer of I/O data can become problematic or, at worst, fail completely.
Various approaches exist to synchronize devices, such as IC chips. Two common approaches are a common clock I/O system and a source synchronous I/O system. A traditional common clock distribution architecture utilizes a common clock source that supplies a clock signal for timing and latching of data. With a common clock system, the clocks at each chip need to be synchronized or timing margin may be compromised. To implement such synchronization, common clock systems usually rely upon board and die solutions implementing a phase-locked loop (PLL) and/or a delay-locked loop (DLL).
In a typical source synchronous I/O system, DLL and PLL circuitry are utilized to generate synchronous strobe information to help latch data at the receiver reliably. While the source synchronous I/O system may employ less complex board designs than the common clock approach, they still utilize complex DLL and PLL circuitry to achieve desired synchronization.